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答案來自：http://answers.yahoo.com/question/index?qid=20090218195707AA8qyoK
transmission delay

In a network based on
packet switching, transmission delay (or store-and-forward delay) is the amount of time required to push all of the packet's bits into the wire. In other words, this is the delay caused by the data-rate of the link.

Transmission delay is a function of the packet's length and has nothing to do with the distance between the two nodes. This delay is proportional to the packet's length in bits,

It is given by the following formula:

DT = N / R

where

DT is the transmission delay

N is the number of bits, and

R is the rate of transmission (say in bits per second)

Most packet switched networks use store-and-forward transmission at the input of the link. A switch using store-and-forward transmission will receive (save) the entire packet to the buffer and check it for CRC errors or other problems before sending the first bit of the packet into the outbound link. Thus store-and-forward packet switches introduce a store-and-forward delay at the input to each link along the packet's route.

http://www.answers.com/transmission%20de…

propagation delay

The time required for a signal to pass through a given complete operating circuit; it is generally of the order of nanoseconds, and is of extreme importance in computer circuits.


The time it takes to transmit a signal from one place to another. Propagation delay is dependent solely on distance and two thirds the speed of light. Signals going through a wire or fiber generally travel at two thirds the speed of light.


Networking
Propagation delay
is defined as the amount of time it takes for a certain number of bytes to be transferred over a medium. Propagation delay is the distance between the two routers divided by the propagation speed.

Propagation delay = d/s where d is the distance and s is the speed.

In electronics, digital circuits and digital electronics, the propagation delay, or gate delay, is the length of time starting from when the input to a logic gate becomes stable and valid, to the time that the output of that logic gate is stable and valid. Often this refers to the time required for the output to reach 50% of its final output level when the input changes. Reducing gate delays in digital circuits allows them to process data at a faster rate and improve overall performance.

The difference in propagation delays of logic elements is the major contributor to glitches in asynchronous circuits as a result of race conditions.

The principle of logical effort utilizes propagation delays to compare designs implementing the same logical statement.