Cypress CYV15G0404DXB四路視頻點(diǎn)到多點(diǎn)通信

Cypress 公司的CYV15G0404DXB是四路獨(dú)立通道HOTLink II收發(fā)器,可以實(shí)現(xiàn)點(diǎn)到點(diǎn)或點(diǎn)到多點(diǎn)通信,在高速連接如光纖,平衡和不平衡銅傳輸線(xiàn)上傳輸數(shù)據(jù),串行連接信號(hào)速率從195M波特到1500M波特.總的吞吐量高達(dá)12Gbps,采用第二代的HOTLink技術(shù),和多種標(biāo)準(zhǔn)如ESCON, DVB-ASI, SMPTE 292M, SMPTE 259M, 以及光通路和GbE (IEEE802.3z)兼容.本文介紹了CYV15G0404DXB的主要特性,方框圖以及發(fā)送與接收通路方框圖, CYV15G0404DXB評(píng)估板電路圖和所用材料清單(BOM)。

The CYV15G0404DXB Quad Independent-Channel HOTLink II Transceiver is a point-to-point or point-to-multipoint communications building block that allows the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at signaling speeds ranging from 195–1500 MBaud per serial link. The independence of each channel provides the ability to simultaneously transport different types of data at different signaling rates across multiple channels.

This user’s guide describes the operation and interface of the CYV15G0404DXB evaluation board. The evaluation board allows users to become familiar with the functionality of the CYV15G0404DXB.

CYV15G0404DXB套件包括:

CYV15G0404DXB-EVAL (the evaluation board)

Dear Customer letter

A CD containing

—CYV15G0404DXB data sheet

—CYV15G0404DXB Evaluation Board User’s Guide

—CYV15G0404DXB application notes

—0404EN.PDA and 0404BYP.PDA files for the DG2020 parallel data generator

—BSDL model

CYV15G0404DXB主要特性:

Quad channel transceiver for 195- to 1500-MBaud serial signaling rate

—Aggregate throughput of up to 12 Gbits/second

Second-generation HOTLink technology

Compliant with multiple standards

—ESCON, DVB-ASI, SMPTE 292M, SMPTE 259M, Fibre Channel and Gigabit Ethernet (GbE) (IEEE802.3z)

—8B/10B coded data or 10 bit uncoded data

Truly independent channels

—Each channel can perform reclocker function

—Each channel can operate at a different signaling rate

—Each channel can transport a different type of data

Selectable input/output clocking options

Internal phase-locked loops (PLLs) with no external PLL components

Selectable differential PECL-compatible serial inputs per channel

—Internal DC-restoration

Redundant differential PECL-compatible serial outputs per channel

—Source matched for 50Ω transmission lines

—No external bias resistors required

—Signaling-rate controlled edge-rates

MultiFrame Receive Framer provides alignment options

—Bit and byte alignment

—Comma or Full K28.5 detect

—Single or Multi-byte Framer for byte alignment

—Low-latency option

Synchronous LVTTL parallel interface

JTAG boundary scan

Built-In Self-Test (BIST) for at-speed link testing

Compatible with

—Fiber-optic modules

—Copper cables

—Circuit board traces

Per-channel Link Quality Indicator

—Analog signal detect

—Digital signal detect

Low-power 3W @ 3.3V typical

Single 3.3V supply

256-ball thermally enhanced BGA

0.25μ BiCMOS technology

圖1.CYV15G0404DXB方框圖

圖2.CYV15G0404DXB發(fā)送通道方框圖

圖3.CYV15G0404DXB接收通道方框圖

圖4. CYV15G0404DXB評(píng)估板外形圖

CYV15G0404DXB評(píng)估板電路圖

圖5.CYV15G0404DXB評(píng)估板電路圖(1)

圖6.CYV15G0404DXB評(píng)估板電路圖(2)

圖7.CYV15G0404DXB評(píng)估板電路圖(3)

圖8.CYV15G0404DXB評(píng)估板電路圖(4)

圖9.CYV15G0404DXB評(píng)估板電路圖(5)

圖10.CYV15G0404DXB評(píng)估板電路圖(6)

圖11.CYV15G0404DXB評(píng)估板電路圖(7)

CYV15G0404DXB評(píng)估板材料清單(BOM):

作者：賽普拉斯半導(dǎo)體 來(lái)源：中華電子網(wǎng)